Data Processing on FPGAs

by Geoffrey Ndu, University of Manchester

FPGAs (Field-Programmable Gate Arrays) are reprogrammable silicon chips that can be used to implement custom execution engines. FPGAs are becoming mainstream. For instance, IBM POWER8 processor has the Coherent Accelerator Processor Interface (CAPI) which allows an FPGA accelerator to coherently attach to the fabric of a POWER8 chip and access up to 1 TB of system memory [1]. Microsoft is using FPGAs to accelerate workloads in the datacenter [2].

In AXLE, we are looking into how the potential power of FPGAs could be harnessed by everyone, especially small and medium firms without the resources of the technology giants, to   speed up analytics on relational databases. We have identified programming FPGAs with software-like languages instead of traditional hardware description languages as a route for database kernel developers to access the power of FPGAS. Programming FPGAs using high level software languages allows a designer to work more productively at a higher level of abstraction and achieve faster time-to-market.

We have explored the trade-offs involved in using high level languages using to program FPGAs in the context of relational databases. The results of our study is detailed in this paper [3]. We are developing CHO [4], [5]; a benchmark suite that could be used to evaluate FPGAs that support programming with OpenCL. OpenCL is an open, royalty-free, parallel programming framework for writing applications that execute across heterogeneous platforms consisting of Central Processing Units (CPUs), Graphics Processing Units (GPUs), FPGAs and other processors. This paper [4] provides more information about our benchmark suite as well as a gentle introduction to computing with FPGAs.

[1]. OpenPOWER CAPI Developer Kit for POWER8

[2]. A. Putnam, A. Caulfield, et al. Reconfigurable Fabric for Accelerating Large-Scale Datacenter Services. In Proceedings of the 41st International Symposium on Computer Archiecture (ISCA 2014).

[3]. O. Abella, G. Ndu, et al. An Empirical Evaluation of High-level Synthesis Languages and Tools for Database Acceleration. In Proceedings of the 24th International Conference on Field Programmable Logic and Applications (FPL 2014).

[4]. G.Ndu, J.Navaridas and M. Lujan. CHO: A Benchmark Suite for OpenCL-based FPGA Accelerators. University Manchester Technical Report UNIMAN-COMP-APT-TR-02-05-2014.

[5]. G.Ndu, J.Navaridas and M. Lujan. CHO: Towards a Benchmark Suite for OpenCL FPGA Accelerators. In Proceedings of the 3rd International Workshop on OpenCL.

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